1. Field of the Invention
The present invention relates to a burn-in and test Method of semiconductor wafers and burn-in boards for use in semiconductor wafer burn-in tests.
2. Description of Prior Arts
Memories, logic circuits and other devices use integrated circuits, and such integrated circuits are produced according to the photo-printing and etching processes, which processes are effected on silicon wafers to form a lot of semiconductor integrated circuits thereon. Then, such silicon wafers are diced to separate the so formed integrated circuits, and finally each and every integrated circuit is packaged. Usually three to four hundred integrated circuits are formed in a single wafer.
A prober-and-tester is used to check all integrated circuits of the silicon wafer one by one, and mark defective integrated circuits with ink, if any, and the so marked integrated circuits are rejected and disposed. At this stage those integrated circuits which have passed the test are separated from each other by dicing the wafer, and connection pins are bonded to the terminals of each silicon chip of integrated circuit. Finally the semiconductor chip is packaged by molding to provide an integrated circuit unit.
The integrated circuit units thus made are subjected to aging prior to marketing. This is necessitated because a large number of the integrated circuit units which have passed required tests are liable to have malfunctions or defects after 1000 hour-long working. Aging has the effect of eliminating such initial malfunctions. Aging is carried out by keeping integrated circuit units at a relatively high temperature (125 degrees Celsius) and by applying a dc voltage thereto for about 100 hours. After aging the integrated circuit units are subjected to a final test, and then the integrated circuit units which have passed the final test can be marketed.
A large number of integrated circuit units, however, are rejected at the final stage after aging, and are disposed. These rejected integrated circuit units have passed required preceding tests, and have passed the bonding, molding and packaging stages, and therefore, disposal of such integrated circuit units is waste of time, labor and expense involved for such preceding stages.
From the angle of saving the preceding treatments vainly performed on integrated circuit units which are finally rejected as defective it is supposed to be advantageous that: silicon wafers each having a lot of integrated circuits formed thereon are subjected to aging process; the so aged silicon wafers are tested by a prober-and-tester to determine which integrated circuits are permissible; the integrated circuits thus found to be permissible are separated by dicing; and finally connection pins are bonded to the terminals of each of the semiconductor chips, and then, all semiconductor chips are packaged to provide integrated circuit units. Also, from the same point of view as mentioned above it is supposed to be advantageous that: "bare" semiconductor chips prior to bonding and packaging are subjected to aging; the so aged, "bare" chips are tested by a prober-and-tester to determine which chips are permissible; and the "bare" chips which passed required tests are subjected to subsequent treatments such as bonding and packaging to provide final products.
As for the former the aging at an early stage necessitates the applying of a required dc voltage to the terminals of each integrated circuit formed in a silicon wafer, for instance by using a wafer prober-and-tester, but the "one-by-one" aging of three to four hundred integrated circuits in the wafer involves much time and labor, and therefore, it is almost impractical.
Incidentally, to meet the demand for the simultaneous aging and testing of numerous integrated circuits in a silicon wafer there has been developed and used a wafer burn-in apparatus which can effect every kind of aging and monitored aging on all integrated circuits in the silicon wafer in a relatively short time, thus permitting a substantial reduction of manufacturing cost for integrated circuits. Also, the aging and testing of integrated circuits prior to dicing permits the rejecting of defective integrated circuits while remaining in the wafer, thus saving required bondings and packagings for integrated circuits which otherwise would be found defective at the final stage after dicing and completing such bondings and packagings.
Such a wafer burn-in apparatus, however, is very complicated because it is designed to use a plurality of printed contact boards in selectively accessing to the bonding pads or terminals each of the numerous integrated circuits formed in the silicon wafer.
The number of bonding pads increases with the increase of the integrated circuits to be formed in the silicon wafer, and accordingly the number of printed contact boards increases, and the contact-to-terminal alignment will be increasingly difficult. Thus, the number of integrated circuits to be formed in a single silicon wafer is limited by the permissible density at which the contacts of the printed contact board are formed so as to be put in contact with the bonding pads each of the integrated circuits in the silicon wafer. Stated otherwise, the wafer burn-in apparatus cannot handle semiconductor wafers each having too many integrated circuits to connect to the wafer burn-in system via the contacts of the associated printed contact boards.
As for the aging of "bare" chips described above there has been developed and used another burn-in apparatus which can effect required function tests, burn-ins, selections and other treatments in the same circumference as packaged chips are subjected to such required treatments.
It uses chip carriers and sockets to accommodate and detachably hold such chip carriers. Each carrier can be loaded with a "bare" chip. The carrier has a self-alignment capability of automatically putting the bonding pads of the "bare" chip in contact with the terminals of the carrier, and when the carrier is put in the socket, the "bare" chip can be connected to the burn-in apparatus.
Advantageously this type of burn-in apparatus requires much less complicated electric connections than the burn-in apparatus for the simultaneous aging and testing of numerous integrated circuits in a silicon wafer. It, however, requires that numerous carriers are loaded with "bare" chips one after another, and this loading work involves much time.
Also, disadvantageously the burn-in apparatus has no means to determine which parts of the original wafer correspond to individual "bare" chips. From the results of the burn-in test, therefore, nobody can tell which part of the silicon wafer is liable to cause what kind of defect.